Licensable IP for communications, RF and video.
Verified FPGA IP cores for AMD and Altera devices, productized from Lorentis defence programmes. Each ships with a testbench, a bit-accurate model, documentation and integration support.
Inside every core.
Select a core to see its architecture. The data flows through the real processing stages of the design, the same blocks you will find in the datasheet.
Download the product briefs.
Full specifications, interfaces, build options and licensing for each core. For evaluation netlists and pricing, contact us.
H.264 Video Encoder IP Core
ITU-T H.264 / ISO/IEC 14496-10 compliant encoder with hardware rate control, low-latency mode and Annex B or MPEG-2 TS output, up to 3840 × 2160.
Download datasheet (PDF) ↓Falcon ISP IP Core
Image signal processor for Bayer CMOS sensors: defect correction, noise reduction, white balance, demosaic, colour correction and gamma, one pixel per clock.
Download datasheet (PDF) ↓A complete package, not just RTL.
We follow the delivery model serious IP buyers expect. Everything your team needs to evaluate, integrate and qualify the core is in the box.
Netlist or source
IEEE-1735 encrypted RTL or netlist by default. Full VHDL or SystemVerilog source is available as an option.
Vendor packaging
IP-XACT for the Vivado IP catalog and Platform Designer components for Quartus, ready to drop into your design.
Bit-accurate models
C/C++ and MATLAB reference models that match the hardware bit for bit, for link-budget and system simulation.
Self-checking testbench
Test vectors and a one-command regression that runs in Questa or the Vivado simulator.
Datasheet & user guide
Resource use per device family, fmax, latency, throughput and, for FEC, BER/FER performance curves.
Reference design
A working demo on real hardware, plus an evaluation build you can test on your own board before you buy.
Need a core that doesn’t exist yet?
We design new FPGA IP to your specification: non-standard waveforms, mission-specific FEC, custom DSP. Typical delivery is 2 to 5 months, depending on complexity.
- Month 0–1 · requirements, architecture, bit-accurate model
- Month 1–3 · RTL design and UVM verification
- Month 2–4 · synthesis, timing closure, hardware bring-up
- Month 3–5 · characterization, datasheet, delivery
IP developmentSimple, royalty-free licensing.
Evaluation
A time-limited encrypted build that runs on your own hardware. Its cost is credited against your purchase.
Single project
One product or programme, unlimited units, royalty-free, with 12 months of support.
Multi-project & source
Site-wide use across products, optional full source code, and ASIC licensing on request.
Try it on your board before you buy.
Tell us your target device and use case. We will send the datasheet and set up an evaluation licence.
- Datasheets and BER curves under NDA
- Integration support from the design team
- Custom configurations on request
- Export classification provided per core