ASIC Design

Custom silicon, end-to-end — from architectural study to tape-out

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ASIC DESIGN

For programs that outgrow off-the-shelf silicon, Lorentis delivers full custom ASIC design. We take you from initial architecture through RTL, verification, DFT, physical design, signoff and tape-out to the leading foundries. Our team's experience spans communication protocol ASICs (Ethernet, MIPI, MIL-STD-1553, ARINC 664), low-power sensor front-ends, mixed-signal designs and high-reliability rad-tolerant flows.

WHAT WE DELIVER

ARCHITECTURE & SPECIFICATION

Block-level architecture, power/area/performance budgeting

RTL DESIGN & IP INTEGRATION

Synthesizable RTL, third-party IP integration

DESIGN VERIFICATION

UVM testbenches, formal proof, coverage closure

DFT & MANUFACTURING TEST

Scan insertion, BIST, JTAG, ATPG vectors

PHYSICAL DESIGN

Floorplanning, placement, routing, timing closure, signoff

TAPE-OUT & PRODUCTION

Foundry hand-off, bring-up support, yield analysis

OUR PROCESS

1

Architecture & Feasibility

System requirements capture, technology node selection, power/area/performance budgeting and risk assessment.

2

RTL + Verification

RTL coding in VHDL/SystemVerilog, IP integration, UVM testbench development and functional coverage closure.

3

DFT Insertion & Synthesis

Scan chain insertion, BIST, JTAG boundary scan, ATPG vector generation and logic synthesis to target library.

4

Physical Design & Signoff

Floorplanning, power planning, place and route, static timing analysis, IR drop, EM and DRC/LVS signoff.

5

Tape-out & Bring-up

Foundry GDS hand-off, first silicon bring-up, characterisation, yield analysis and production test support.

PROCESS NODES

180nm

65nm

40nm

28nm FD-SOI

16nm

7nm
Start an ASIC project →
  • Process nodes:

    180nm → 7nm across leading foundries

  • Standards:

    ISO 26262 · DO-254 · MIL-STD-883

  • Deliverables:

    GDS · netlist · testbenches · documentation

  • Contact:

    Start a technical discussion →