Custom silicon, from architecture to packaged chips.
We design your ASIC in Istanbul on licensed Cadence and Synopsys flows. We tape out through X-FAB and TSMC, and manage packaging, assembly and test in Europe. One point of contact, from specification to chips in your hands.
Watch a chip get built.
After RTL is verified, the design is floorplanned, placed, clock-tree synthesized and routed on the target process, then signed off for DRC, LVS and timing before the GDSII goes to the foundry.
Designed in Türkiye. Fabricated at world-class fabs. Assembled in Europe.
Follow a chip from our design centre in Istanbul to the foundry, through packaging and test in Europe, to your facility. Choose the foundry route.
Every step to a chip you can solder.
Finished wafers are probed, diced, attached, wire-bonded, moulded, marked and tested. We coordinate each step with qualified European partners.
Wafer
Cleanroom
Silicon
Packaged partThe right node for your chip.
We work across the full X-FAB portfolio for analog, mixed-signal, high-voltage, sensor and automotive silicon, and on TSMC 65 nm and 90 nm for digital-heavy designs.
| Foundry · node | Technology | Typical use |
|---|---|---|
| TSMC 65 nm | Logic, mixed-signal, RF CMOS | DSP, communications SoCs, digital-heavy designs |
| TSMC 90 nm | Logic, mixed-signal CMOS | Controllers, interface and mixed-signal ASICs |
| X-FAB 110 nm | XT011 · BCD-on-SOI | Automotive and high-temperature power management |
| X-FAB 130 nm | XR013 · RF SOI | RF switches and front-end modules |
| X-FAB 180 nm | XH018 · XP018 · XT018 · XS018 | Mixed-signal, high-voltage, BCD-on-SOI, image sensors |
| X-FAB 350 nm | XH035 · XA035 · XO035 | Sensor, high-voltage, optoelectronics, automotive |
| X-FAB 1.0 µm | XDH10 · XDM10 · BCD-on-SOI | Ultra-high-voltage drivers up to 625 V |
| X-FAB MEMS · SiC · GaN | Specialty processes | MEMS sensors, power semiconductors |
Access to TSMC nodes is through European multi-project wafer programmes.
One team from spec to silicon.
Architecture & specification
System partitioning, IP selection, power, performance and area targets, and the choice of process and package.
RTL design & verification
SystemVerilog RTL, UVM verification, formal checks and FPGA prototyping of the ASIC design before tape-out.
Physical design
Synthesis, DFT and scan insertion, floorplanning, place and route, and clock-tree synthesis on Cadence and Synopsys flows.
Sign-off
Static timing, IR drop and electromigration, DRC and LVS sign-off, then GDSII hand-off to the foundry.
Tape-out & foundry
Tape-out coordination with X-FAB and TSMC, on MPW shuttles for prototypes and dedicated runs for production.
Packaging, assembly & test
Package design, assembly, wafer and final test with European partners, plus bring-up of first silicon in our lab.
Turn your FPGA design into silicon.
Whether you are cutting unit cost, power or size, or protecting your IP in silicon, we will help you choose the node, the package and the path to first silicon.
- Feasibility, cost and schedule estimate
- MPW prototyping for low first-silicon cost
- X-FAB and TSMC process access
- Designed at Teknopark İstanbul