DESIGN VERIFICATION

Verification is often 60–70% of an IC project's effort. Lorentis provides verification as a standalone specialty because the methods and mindset are genuinely different from design. Our team builds UVM environments, writes directed and constrained-random tests, closes functional and code coverage, and for the most demanding projects, proves correctness with formal methods. We report verification metrics so you always know where confidence stands.


WHAT WE DELIVER


VERIFICATION PLANNING

Testplan capture, coverage model definition

UVM / UVVM / OSVVM ENVIRONMENTS

Reusable, modular, configurable

CONSTRAINED-RANDOM TESTING

Intelligent stimulus shaping and test generation

FORMAL VERIFICATION

Property checking, equivalence, X-propagation

COVERAGE CLOSURE

Functional, code, assertion, toggle coverage

VERIFICATION IP

Interface VIPs for Ethernet, PCIe, AXI, MIPI, MIL-STD-1553


Talk to our verification team →


  • Methodologies:

    UVM · UVVM · OSVVM · Formal · PSS

  • VIP coverage:

    Ethernet · PCIe · AXI · MIPI · MIL-STD-1553

  • Tools:

    Questa · VCS · Xcelium · JasperGold · SymbiYosys

  • Contact:

    Start a technical discussion →